A dynamic random access memory (DRAM) is usually able to store two different values, logical zero and logical one. The memory is volatile, in that once power is removed from the memory, it loses its stored value. The memory must be periodically refreshed in order it to maintain the value stored. The period of time that can elapse before the memory must be refreshed is known as the retention time of the memory, which is the length of time that the memory can retain its stored logical value.
FIG. 1 shows an embedded DRAM 100 having a transfer gate transistor and a P-channel charge storage capacitor. The embedded DRAM 100 includes a metal oxide semiconductor (MOS) capacitor that includes a polysilicon plate 114, and a storage node 108 formed with a P+ implant 106. A voltage Vbb 122, such as −0.3 volts (V), is biased at the poly plate 114 to have the storage node 108 operate in the inversion region to maintain a capacitance. Unfortunately, this shallow bias is close enough to the threshold voltage Vt of the MOS capacitor, and might bias the capacitor in the depletion region and turn off the channel between the storage node 108 and the capacitor, causing incomplete data writing. This causes poor retention time of the logically stored value in the capacitor, especially for the writing and storage of a logical value zero.
The embedded DRAM 100 also includes an N well 102, in which there are P+ implants 104 and 112. A bit line 118 is connected to the bit line contact P+ implant 104. A transfer gate 116 is connected to a voltage Vbb/Vpp 120, where Vbb is the turn-on voltage for the DRAM 100, and Vpp is the turn-off voltage. The N well 102 is biased at the voltage Vdd 124. There is a region of shallow trench isolation (STI) 110 underneath the poly plate 114. A threshold current Ith 126 flows from the P+ implant 106 to the P+ implant 104. A junction leakage current Ij 128 flows down from the P+ implant 106 to the N well 102. A gate current 130 and a gate current 132 flow from the P+ implant 106 to the poly plate 114 and the transfer gate 116, respectively.
The poor retention time of the logically stored value in the capacitor can be considered as being related to how large the junction leakage current Ij 128 is. The junction current Ij 128 is in turn related to the doping profile and the junction bias. The NVY (P-type) implant proposed in this invention counteract the N-Well dosage, effectively reducing the threshold voltage and increase the charges of writing into capacitor. The P-implant also degrades the gradient of doping profile between the storage node and NW that can effectively decrease the junction leakage. So the retention time of memory can be improved.
FIG. 2 shows the equivalent circuit observed from the storage node 108. The memory 100 includes the storage node 108, the voltage Vbb 122, the MOS capacitor 204, and the resistance 202. The resistor 202 accounts for the channel resistance of the capacitor of FIG. 1 and the capacitor 204 having the STI 110 of FIG. 1 and the poly plate 114 of FIG. 1. Thus, desirably decreasing the resistance 202 by decreasing the Vt of the capacitor and increasing the current to the capacitor 204 allows for enhanced retention time of the MOS capacitor.
FIGS. 3 and 4 show prior art approaches for accomplishing this within the memory 100. In FIG. 3, a P− depletion layer 302 is formed under the poly plate 114 of the capacitor. This layer has better capability for data writing, but increases the junction leak current Ij 128 of FIG. 1 at the same time due to a larger p-n junction area having been formed. In FIG. 4, pocket P− implants 402 and 404 are added around the P+ implants 104 and 106, respectively, accomplishing the same objective. However, this approach does not work for small devices, less than 0.1 micron in feature size, since it would increase inevitably the source-drain punch-through possibility, and thus is not desirable.
Therefore, there is a need to increase the retention time of the MOS capacitor of an embedded DRAM. Such an increase should be accomplished without P− implants as is done in the memory 100 of FIG. 3, which can cause larger junction leakage. Such an extra should also be accomplished without pocket P− implants as is done in the memory 100 of FIG. 4, which increases the possibility of punch-through for small devices. For these and other reasons, there is a need for the present invention.